1. Field of the Invention
This invention relates in general to computers, and in particular to top level cache design.
2. Prior Art
The survey article[1] covers cache prefetching and many other aspects of cache memory design.
References 2, 3, and 4 describe prior work leading up to the present invention.
A conventional cache operates without the benefit of the information available to a compiler.
Thrashing occurs when the use of two or more blocks contend for the single available block in a direct mapped cache. Restated, thrashing occurs when needed information in a block is deleted to to make room for needed information in another block, later, the original block must be reloaded.
The objects of the present invention are to reduce the frequency of memory accesses by grouping the memory accesses into fewer accesses but with more words per access, reduce thrashing by using cache subsetting to separate cache uses, reduce cache access time by using cache addresses to access the cache, provide cache like behavior within the subsets, and provide an efficient method to timeshare the processor.
[1] Veljko Milutinovic, David Fura, Walter Helbig, Joseph Linn, "Architecture/Compiler Synergism in GaAs Computer Systems" Computer May 87, pp 84-90. PA0 [2] Stanley Lass "Wide Channel Computers" Computer Architectue News June 1987 PA0 [3] Stanley Lass "Multiple Instructions/Operands per Access to Cache Memory" Computer Architectue News March 1988 PA0 [4] Stanley Lass "Shared Cache Multiprocessing with Pack Computers" Computer Architectue News June 1988